Packet-based integrated circuit dynamic random access memory device incorporating an on-chip row register cache to reduce data access latencies

ABSTRACT

A packet-based dynamic random access memory (“DRAM”) device incorporating an on-chip row register cache which is functional to reduce the initial device latency, reduce “page miss” latency and reduce chip layout overhead by reducing bus sizes and the level of required multiplexing and demultiplexing compared to Rambus® Direct RDRAM™ (trademarks, of Rambus, Inc., Mountain View, Calif.) devices. In accordance with an embodiment of the present invention, the row register cache and a separate write path, or bus, are integrated into each DRAM bank serving to improve DRAM latency parameters and pipeline burst rate. The row register holds “read” data during burst reads to allow hidden precharge and same bank activation to minimize “page miss” latency. The faster pipelined burst rate simplifies Direct RDRAM multiplexer/demultiplexer logic and reduces internal data bus size by 50%.

BACKGROUND OF THE INVENTION

[0001] The present invention relates, in general, to the field ofintegrated circuit (“IC”) dynamic random access memory (“DRAM”) devices.More particularly, the present invention relates to a packet-based DRAMmemory device incorporating an on-chip row register cache which isfunctional to reduce overall data access latencies, especially withrespect to “page misses”.

[0002] A new type of volatile random access memory devices has beenrecently introduced which uses low pin count interfaces operating athigh clock rates to multiplex memory control, address, and data in andout of the chip. These so called “protocol-based” or “packet-based”memories have the benefit of delivering high potential bandwidth in alow-pin count single chip IC package. This approach is particularlyinteresting for small systems containing just a single processorcomponent and a single memory device.

[0003] The Rambus® DRAM (“RDRAM™” trademarks of Rambus, Inc., MountainView, Calif.) was the first of several proposed packet-based DRAMdevices. The most current version of this product was developed inconjunction with Intel Corporation, Santa Clara, Calif. and is calledthe Direct Rambus DRAM (or “DRDRAM”). See for example, Rambus®Technology Overview, Rambus, Inc., Aug. 23, 1999 and Direct RDRAM™Advance Information 64/72-Mbit (256K×16/18×16d) Rambus, Inc. Aug. 3,1998, the disclosures of which are specifically incorporated herein bythis reference. The Direct RDRAM has been optimized to allow concurrentcommand, address, and data packets to be transferred to improve theefficiency of the bus interface.

[0004] Nevertheless, the DRDRAM presents several operational limitationswhich prevent its optimum performance and cost effectiveness. Firstly,the DRDRAM architecture imposes significantly larger chip sizes than arefound in traditional DRAM components. This size increase results fromthe need to multiplex and demultipex data and addresses at the businterface. Specifically, the current DRDRAM embodiment has a relativelycomplex eight way multiplexer and demultiplexer interface to theexternal data bus. This level of multiplexing is determined by theexternal data bus size and pipelined data speed of the core DRAM memorybanks. The 18 bit external data bus is specified at an 800 MHz data rateand the DRAM core must deliver a 1.6 GB/sec. bandwidth. Current DRAMcores can deliver a new data-word every 10 ns or a 100 MHz data rate.For this core, the internal DRAM bus must be eight times 18 bits (or 144bits) to deliver the specified data rate.

[0005] Secondly, multiplexing address and data buses increases randomaccess latency compared to synchronous DRAM (“SDRAM”). At 800 MHz,address packet delays are 10 ns and data packet delays for a 64 bitequivalent word are 5 ns. Consequently, every SDRAM random accessparameter is degraded by 15 ns in Direct RDRAM.

[0006] Thirdly, standard DRAM core exhibits relatively long latency onsame bank “page misses” which reduce bus efficiency. The standard DRAMcore uses page mode operation, which means that data is held in the DRAMsense amplifiers during random access within a page. If a request foranother page in the same bank occurs, the DRAM must precharge and thenanother row must be randomly accessed into the sense amps. This “pagemiss” can take on the order of 70 ns in current DRAM technology. A “pagemiss” greatly reduces bus efficiency and delivered bandwidth. Themaximum bandwidth for the device is equal to four data words (64 bit) at5 ns/data word, which is 20 ns for 32 bytes, or 1600 MB/sec. On theother hand, the worst case bandwidth (in the case of a “page miss”,Read-to-Read) is 77.5 ns (“page miss”) plus three data word (64-bit)times at 5 ns/data word which equals 92.5 ns for 32 bytes or 338 MB/sec.Thus, it can be seen that Direct RDRAM bus efficiency is reduced from100% to 21% under continuous random “page misses”while deliveredbandwidth is reduced from 1600 MB/Sec to 338 MB/Sec.

SUMMARY OF THE INVENTION

[0007] Enhanced Memory Systems, Inc., a subsidiary of RamtronInternational Corporation, Colorado Springs, Colorado and assignee ofthe present invention, has long been a pioneer in defining low latency,high efficiency DRAM core architectures based on its proprietary EDRAM®core technology (EDRAM® is a registered trademark of Enhanced MemorySystems, Inc., Colorado Springs, Colo.) See for example, U.S. Pat. Nos.5,699,317, 5,721,862, and 5,887,272, the disclosures of which arespecifically incorporated herein by this reference, and which disclosecertain implementations of the application of this technology tostandard DRAM architectures.

[0008] Disclosed herein are extensions of this EDRAM technologyimplemented to enhance packet-based DRAM architectures, such as DirectRDRAM, to reduce the initial device latency, reduce “page miss” latencyand reduced chip layout overhead by reducing bus sizes and the level ofrequired multiplexing and demultiplexing.

[0009] In accordance with an embodiment of the present inventiondisclosed herein, a row register (or “cache”) and separate write path,or bus, are integrated into each DRAM bank. This enhanced DRAMarchitecture, improves DRAM latency parameters and pipeline burst rate.The row register holds “read” data during burst reads to allow hiddenprecharge and same bank activation to minimize “page miss” latency. Thefaster pipelined burst rate simplifies Rambus RDRAMmultiplexer/demultiplexer logic and reduces internal data bus size by50%.

[0010] Particularly disclosed herein is a packet-based integratedcircuit device comprising at least one dynamic random access memory bankhaving associated row and column decoders for specifying memorylocations therein in response to externally supplied row and columnaddresses. The device includes at least one sense amplifier circuitcoupled to the column decoder for reading data from the memory bank, arow register coupled to the sense amplifier circuit for retaining atleast a portion of the data read out from the memory bank, a multiplexercircuit coupling the row register to an external data bus for supplyingthe read out data thereon and a demultiplexer circuit coupling theexternal data bus to the sense amplifier circuit for supplying dataapplied to the external data bus to the memory bank.

BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The aforementioned and other features and objects of the presentinvention and the manner of attaining them will become more apparent andthe invention itself will be best understood by reference to thefollowing description of a preferred embodiment taken in conjunctionwith the accompanying drawings, wherein:

[0012]FIG. 1 illustrates a conventional Direct Rambus DRAM architectureillustrating the need for a 144 bit internal data bus and 8:1multiplexing and de-multiplexing to a bi-directional 18 bit externaldata bus;

[0013]FIG. 2 illustrates a packet-based DRAM memory device in accordancewith an embodiment of the present invention incorporating one or moreon-chip registers (or “cache”) which retains at least a portion of dataread out from the DRAM banks and having a 72 bit internal data bus and4:1 multiplexing and de-multiplexing to a bi-directional 18 bit externaldata bus;

[0014]FIG. 3A is a simplified timing diagram of the row, column and dataactivity for a “page miss” occurring between two consecutive “read”transactions for the conventional Direct RDRAM of FIG. 1;

[0015]FIG. 3B is a corresponding simplified timing diagram of the row,column and data activity for a “page miss” occurring between twoconsecutive “read” transactions for the memory device of FIG. 2 inaccordance with the present invention;

[0016]FIG. 4A is an additional simplified timing diagram of the row,column and data activity for a “page miss” occurring between consecutive“read” and “write” transactions for the conventional Direct RDRAM ofFIG. 1; and

[0017]FIG. 4B is a corresponding simplified timing diagram of the row,column and data activity for a “page miss” occurring between consecutive“read ” and “write” transactions for the memory device of FIG. 2.

DESCRIPTION OF A PREFERRED EMBODIMENT

[0018] With reference now to FIG. 1, a conventional Direct Rambus DRAMdevice 10 architecture is shown. The Direct RDRAM device 10 comprises,in pertinent part, one or more DRAM banks 12 and associated row decoders11 and column decoders 13. A number of DRAM sense amplifiers 14 couplethe DRAM banks 12 through the column decoders 13 to an internal 144 bitdata bus as shown.

[0019] Access to the memory locations in the DRAM banks 12 is had via anaddress bus coupled to 8 to 1 row address demultiplexers 16 and 18 forsupplying row and column addresses to the row decoders 11 and columndecoders respectively. Control signals for the Direct RDRAM device 10are also supplied externally through an additional 8 to 1 commanddemultiplexer 20.

[0020] The 144 bit internal data bus provides data read from the DRAMbanks 12 to an 8 to 1 multiplexer 22, the output of which is selected bygates 24 for output from the Direct RDRAM 10 on an 18 bit bidirectionaldata bus 26. Data to be written to the Direct RDRAM device 10 issupplied on the 18 bit data bus 26 and selected by gates 28 to an 8 to 1demultiplexer 30 having an associated write buffer 32 for temporaryretention of data to be ultimately written to the DRAM banks 12. Theoutput of the write buffer 32 is supplied to the DRAM sense amplifiers14 through the internal 144 bit data bus. As can be seen, the DirectRDRAM device 10 requires a relatively wide 144 bit internal data bus inaddition to the provision of 8:1 multiplexing and demultiplexing to thebidirectional 18 bit external data bus 26.

[0021] With reference additionally now to FIG. 2, a packet-based DRAMmemory device 50 in accordance with an embodiment of the presentinvention is shown. The memory device 50 includes DRAM banks 52,associated row decoders 51 and column decoders 53 together with DRAMsense amplifiers 54 as in the conventional Direct RDRAM device 10 shownin the preceding figure. However, the memory device 50 furtherincorporates one or more on-chip row registers (or “cache”) 56 whichretain at least a portion of data read out from the DRAM banks 52.

[0022] Access to the memory device 50 is afforded through respective rowand column address demultiplexers coupled to an external address bus forsupplying row and column addresses to the row decoders 51 and columndecoders 53. Likewise, control signals for the memory device 50 aresupplied through a command demultiplexer 62.

[0023] At least a portion of the data read out from the DRAM banks 52 ismaintained in the row register cache 56 and is then supplied on a 72 bitinternal read data bus to a 4 to 1 multiplexer 64. The output of the 4to 1 multiplexer 64 is then selected by gates 66 for output on anexternal 18 bit data bus 68. Data to be written to the memory device 50is supplied on the 18 bit data bus 68 and selected through gates 70 forinput to a 4 to 1 demultiplexer 72 having an associated write buffer 74.Data to be written to the DRAM banks 52 is temporarily retained in thewrite buffer 74 for application to the DRAM sense amplifiers 54 over a72 bit internal write data bus. As can be seen, the memory device 50includes a row register 56 for faster access to data in addition to arelatively smaller 72 bit internal data bus and simplified 4:1multiplexing and de-multiplexing to the bi-directional 18 bit externaldata bus 68 while simultaneously presenting an external interfaceequivalent to that of the conventional Direct RDRAM device 10 of FIG. 1.

[0024] The memory device 50 appears externally identical to aconventional Direct RDRAM 10 (FIG. 1) but has a different DRAM coreimplementation using a set of row register caches 56 tightly integratedwith the DRAM sense amplifiers 54 and a separate write path that allowswrites to go directly to the sense amplifiers 54. The integrated rowregister cache 56 supports a faster 5 ns (or 200 MHz) pipelined burstrate that allows the internal data path to be reduced to 72 bits (from144 bits in the conventional Direct RDRAM 10) and a simpler 4 to 1multiplexer 64 and demultiplexer 72 at the data interface.

[0025] In addition to simplifying the data path, multiplex anddemultiplexing logic and reducing the internal bus wiring by 50%, theenhanced DRAM core of the memory device 50 improves basic DRAMparameters as shown in the following Table 1: TABLE 1 ConventionalParameter DRDRAM 10 Memory Device 50 t_(RC) 70 ns 35 ns t_(RAS) 50 ns 25ns t_(RP) 20 ns 15 ns t_(RR) 20 ns 15 ns t_(RCD) 22.5 ns   15 ns t_(RAC)45 ns 25 ns t_(CAC) 20 ns 10 ns t_(CWD) 15 ns 10 ns t_(Packet) 10 ns 10ns t_(RTR) 20 ns 15 ns t_(OFFP) 10 ns  0 ns

[0026] With respect to the foregoing Table 1, t_(RC) is the row cycletime; t_(RAS) is the row address strobe (“RAS”)-asserted time; t_(RP) isthe row precharge time; t_(RR) is the RAS-to-RAS time; t_(RCD) is theRAS to column address strobe (“CAS”) delay time; t_(RAC) is the RASaccess delay time; t_(CAC) is the CAS access delay time; t_(CWD) is the10 CAS write delay time; t_(Packet) is the length of the packet; t_(RTR)is the interval from a column operation (“COLC”) packet with a writeprecharge (“WR”) command to COLC packet which causes retire; andt_(OFFP) is the interval from COLC packet with a read precharge (“RDA”)command.

[0027] These improvements in DRAM core speed reduce the impact of theAddress/Command and data packet delays by at least 10 ns and 5 nsrespectively.

[0028] Row Access Time

=t _(Packet) +t _(RCD) +t _(CAC)+0.5*t _(Packet)

=10 ns+22.5 ns+20 ns+5 ns=57.5 ns

[0029] for the conventional Direct DRDRAM 10;

=10 ns+15 ns+10 ns+5 ns=40 ns

[0030] for the memory device 50.

[0031] Row Access Improvement

=(57.5 ns−40 ns)/40 ns=44%

[0032] due to the row register cache 56 and DRAM banks 52 core.

[0033] Column Access Time

t _(Packet) +T _(CAC)+0.5*t _(Packet)

=10 ns+20 ns+5 ns=35 ns

[0034] for the conventional Direct DRDRAM 10;

=10 ns+10 ns+5 ns=25 ns

[0035] for the memory device 50.

[0036] Column Access Time Improvement

=(35 ns−25 ns)/25 ns=40%

[0037] due to the row register cache 56 and DRAM banks 52 core.

[0038] The fast EDRAM Core of the memory device 50 also improves thelatency of page misses following write cycles:

[0039] Page Miss (Write-to-Read)

=0.5*t _(Packet) +t _(RP) +t _(RCD) +t _(CAC)+0.5*t _(Packet)

=5 ns+20 ns+22.5 ns+20 ns+5 ns=72.5 ns

[0040] for the conventional Direct RDRAM 10;

=5 ns+15 ns+15 ns+10 ns+5 ns=50 ns

[0041] for the memory device 50.

[0042] Pass Miss (Write-to-Read) Improvement

=(72.5 ns−50 ns)/50 ns=45%

[0043] due to the row register cache 56 and DRAM banks 52 core.

[0044] Page Miss (Write-to-Write)

=0−5*t _(Packet) +t _(RP) +t _(RCD) +t _(CWD)+0.5*t _(Packet)

=5 ns+20 ns+22.5 ns+15 ns+5 ns=67.5 ns

[0045] for the conventional Direct RDRAM 10;

=5 ns+15 ns+15 ns+10 ns+5 ns=50 ns

[0046] for the memory device 50.

[0047] Page Miss (Write-to-Write) Improvement

=(67.5 ns−50 ns)/50 ns=35%

[0048] due to the row register cache 56 and DRAM banks 52 core.

[0049] In addition to faster DRAM core architecture, the memory device50 architecture allows hidden precharge and a same Row activationfeature that results from the row register cache 56 holding the readdata during burst reads. This caching allows concurrent precharge androw activation functions not allowed by the Direct RDRAM device 10 core.

[0050] In the exemplary embodiment of the memory device 50 shown, theDRAM core may be constructed with any number of DRAM bank 12 arrayblocks. Each array block has associated sense amplifiers 54, a rowregister cache 56, and separate logic path to allow write operations togo to the sense amplifiers 54 and read operations to be from the rowregister cache 56, which may comprise static random access memory(“SRAM”) or other high speed memory. The DRAM banks 52 and integratedrow register cache 56 interface with a 72 bit internal data bus which iscoupled to a data path multiplexer 64 and demultiplexer 72 logic at thechip interface. During read data transfers, the DRAM banks 52 withintegrated row register cache 56 places 72 bits of data (4 data words)on the internal data bus every 5 ns. The multiplexer 64 logicsequentially selects one data word to the output data bus 68 every 1.25ns. The conventional Rambus interface of the Direct RDRAM device 10operates at a 400 MHz (2.5 ns clock cycle) rate and data is placed onthe output data bus 26 (FIG. 1) on both the rising and falling edge ofthe clock.

[0051] During writes, data is input to the demultiplexer 72 logic of thememory device 50 every 1.25 ns (rising and falling edges of the clock).The write buffer 74 accumulates 4 data words every 5 ns. This writebuffer 74 is double buffered so that 72 bit of write data is written tothe selected DRAM bank 52 every 5 ns while additional write data isbeing input to the primary buffer stage.

[0052] Read Operations

[0053] A read operation is initiated by a row Packet on the row inputbus. The row address and command are multiplexed into the chip on therising and falling clock edges at a 1.25 ns rate. A total of four clockcycles are necessary to input the row Packet and command (10 ns). Oncethe row Packet is input and the command decoded, the DRAM bank 52 isselected and the selected row address is read into the sense amplifiers54 of that bank after the time tRCD (15 ns). In parallel with the rowaccess, a column address and read command are multiplexed over thecolumn address bus during four clock cycles. It is timed to arrive aftert_(RCD). Once the read command is executed, the sense amplifier 54 datais latched into the row register cache 56 for the selected bank and 72bits of data is transferred to the output multiplexer 64 over the nextfour clock periods. At the end of this period, the row register cache 56is latched and an additional 72 bit words are transferred to themultiplexer 64 every two clock cycles (5 ns). If the read command isissued with an auto precharge or if a manual precharge is placed on therow address bus during the Packet time following the column readcommand, the DRAM bank 52 will enter precharge four clocks (1 Packetdelay, t_(Packet)) following the read command. The precharge time(t_(RP)) occurs while data is being transferred to the multiplexer 64from the row register cache 56. The entire precharge delay is hiddenduring a two Packet data transfer (32 byte transfer).

[0054] Once the precharge time is complete, it is possible to begin thenext access to the same bank by another row address, bank activatecommand on the multiplexed row address bus. This information can betimed to initiate the command as soon as the t_(RP) time is met for a 32byte data transfer and one half of a Packet (5 ns) of the row-to-columndelay can be hidden to reduce “page miss” latency. For longer transfers,the entire row-to-column delay can be hidden. The combination of hiddenprecharge and hidden same bank activation reduces the “page miss”read-to-read latency from 77.5 ns in the conventional Direct RDRAMdevice 10 (FIG. 1) to 25 ns for the memory device 50 (FIG. 2).

[0055] Write Operations

[0056] A write operation is initiated by a row Packet with bank activatecommand on the row bus. The information is clocked on four clock cycles,or 10 ns. At the end of the packet transfer, the command is decoded, theselected bank is activated and the row address is read to the senseamplifiers 54 in a time t_(RCD). The column address packet with writecommand is transferred in parallel with t_(RCD). As soon as it isreceived, the specified column address in the sense amplifiers 54 isselected and write data can begin being input to the demultiplexer 72.After a time t_(CWD), data packets are input to the write buffer 74.

[0057] After every two clock cycles (5 ns), data is written over the 72bit internal bus to the select sense amplifier 54 location, the columnaddress is incremented and another 72 bit word is written each 5 nsperiod. As soon as the last packet is received, a precharge command maybe issued (or precharge will automatically begin on write aauto-precharge command) a one half packet delay (5 ns) after the lastdata input. This restores data to the DRAM banks 52 and readies the DRAMfor the next cycle.

[0058] With reference additionally now to FIG. 3A, a simplified timingdiagram of the row, column and data activity for a “page miss” occurringbetween two consecutive “read” transactions for the conventional DirectRDRAM device 10 of FIG. 1 is shown.

[0059] It should be noted that the Direct RDRAM device 10 keeps columndata in the sense amplifiers 14 of the DRAM. The precharge commandcannot initiate the precharge cycle on a “page miss” until time,t_(OFFP), after the last data packet. The combination of late prechargeand slow DRAM core parameters results in long “page miss” latency andpoor bus efficiency for same bank “page misses”.

[0060] With reference additionally now to FIG. 3B, a correspondingsimplified timing diagram of the row, column and data activity for a“page miss” occurring between two consecutive “read” transactions forthe memory device 50 of FIG. 2 in accordance with the present inventionis shown.

[0061] As shown, the memory device 50 can begin a precharge command inthe packet following the column read command. This is possible since theread page is latched into the row register cache 56 at the end of onepacket delay (10 ns) allowing DRAM bank 52 precharge to occur during thedata burst. It should also be noted that the next random row packet canbegin before the completion of the packets. In this example, one halfpacket delay (5 ns) of the row to column delay is eliminated from the“page miss” latency.

[0062] The following is a comparison of the “page miss” (Read-to-Read)latency between the Direct RDRAM device 10 (FIG. 1) and the memorydevice 50 (FIG. 2) of the present invention:

[0063] Page Miss (Read-to-Read)

=t _(OFFP) +t _(RP) +t _(RCD) +t _(CAC)+0.5*t _(Packet)

=10 ns+20 ns+22.5 ns+20 ns+5 ns=77.5 ns

[0064] for the Direct RDRAM 10;

=t _(RCD)−0.5 t _(Packet) +t _(CAC)+0.5*t _(Packet)

=15 ns−5 ns+10 ns+5 ns=25 ns

[0065] for the memory device 50.

[0066] Page Miss Improvement

=(77.5 ns−25 ns)/25 ns=210%

[0067] due to the row register cache 56 and DRAM banks 52 core speedplus the hidden precharge plus the hidden same bank activation feature.The hidden precharge and same bank activation features also reduce “pagemiss” latency for write cycles following a read as will be more fullydescribed hereinafter.

[0068] With reference additionally now to FIG. 4A, an additionalsimplified timing diagram of the row, column and data activity for a“page miss” occurring between consecutive “read” and “write”transactions for the conventional Direct RDRAM device 10 of FIG. 1 isshown.

[0069] Since the Direct RDRAM device 10 holds data in the senseamplifiers 14 during a burst read, the precharge command does not occuruntil t_(OFFP) after the last read data. The DRAM banks 12 memory mustthen precharge and another row must be accessed to the sense amplifiers14 before data can be written.

[0070] With reference additionally now to FIG. 4B, a correspondingsimplified timing diagram of the row, column and data activity for a“page miss” occurring between consecutive “read” and “write”transactions for the memory device 50 of FIG. 2 is shown.

[0071] Page Miss Latency (Read-to-Write)

=t _(OFFP) +t _(RP) +t _(RCD) +t _(CWD)+0.5*t _(Packet)

=10 ns+20 ns+22.5 ns+15 ns+5 ns=72.5 ns

[0072] for the conventional Direct RDRAM 10;

=t _(RCD)−0.5*t_(Packet) +t _(CWD)+0.5*t _(Packet)

=15 ns−5 ns+10 ns+5 ns=25 ns

[0073] for the memory device 50.

[0074] Page Miss Improvement (Read-to-Write)

=72.5 ns−25 ns/25 ns=190%

[0075] due to the row register cache 56 and DRAM banks 52 core plus thehidden precharge and hidden same bank activation.

[0076] As can be seen, the use of the EDRAM core architecture in thememory device 50 in conjunction with the conventional Rambus DirectRDRAM architecture or other packet-based DRAM devices provides at leastthe following benefits:

[0077] 1) Reduction in on-chip overhead:

[0078] Reduces internal data path from 144 bits to 72 bits; and

[0079] Reduces the multiplexer/demultiplexer logic from 8 to 1 to 4 to1.

[0080] 2) Reduction in initial latency:

[0081] Reduces initial latency of conventional Direct RDRAM;

[0082] Reduces row access time from 57.5 ns to 40 ns (44%); and

[0083] Reduces column access time from 35 ns to 25 ns (40%).

[0084] 3) Reduction of same bank “page miss” latency of conventionalDirect RDRAM:

[0085] Reduces read to read “page miss” from 77.5 ns to 25 ns (210%);

[0086] Reduces read to write “page miss” from 72.5 ns to 25 ns (190%);

[0087] Reduces write to read “page miss” from 72.5 ns to 50 ns (45%);and

[0088] Reduces write to write “page miss” from 67.5 ns to 50 ns (35%).

[0089] While there have been described above the principles of thepresent invention in conjunction with specific device structure it is tobe clearly understood that the foregoing description is made only by wayof example and not as a limitation to the scope of the invention.Particularly, it is recognized that the teachings of the foregoingdisclosure will suggest other modifications to those persons skilled inthe relevant art. Such modifications may involve other features whichare already known per se and which may be used instead of or in additionto features already described herein. Although claims have beenformulated in this application to particular combinations of features,it should be understood that the scope of the disclosure herein alsoincludes any novel feature or any novel combination of featuresdisclosed either explicitly or implicitly or any generalization ormodification thereof which would be apparent to persons skilled in therelevant art, whether or not such relates to the same invention aspresently claimed in any claim and whether or not it mitigates any orall of the same technical problems as confronted by the presentinvention. The applicants hereby reserve the right to formulate newclaims to such features and/or combinations of such features during theprosecution of the present application or of any further applicationderived therefrom.

What is claimed is:
 1. A packet-based integrated circuit devicecomprising: at least one dynamic random access memory bank havingassociated row and column decoders for specifying memory locations insaid at least one dynamic random access memory bank in response toexternally supplied row and column addresses; at least one senseamplifier circuit coupled to said column decoder for reading data fromsaid at least one dynamic random access memory bank; a row registercoupled to said at least one sense amplifier circuit for retaining atleast a portion of said data read out from said at least one dynamicrandom access memory bank; a multiplexer circuit coupling said rowregister to an external data bus for supplying said at least a portionof said read out data thereon; and a demultiplexer circuit coupling saidexternal data bus to said at least one sense amplifier circuit forsupplying data applied to said external data bus to said at least onedynamic random access memory bank.
 2. The integrated circuit device ofclaim 1 wherein said multiplexer circuit is coupled to said row registerby means of an internal read data bus.
 3. The integrated circuit deviceof claim 2 wherein said internal read data bus is less than 144 bitswide.
 4. The integrated circuit device of claim 3 wherein said internalread data bus is 72 bits wide.
 5. The integrated circuit device of claim1 wherein said demultiplexer circuit is coupled to said at least onesense amplifier circuit by means of an internal write data bus.
 6. Theintegrated circuit device of claim 5 wherein said internal write databus is less than 144 bits wide.
 7. The integrated circuit device ofclaim 6 wherein said internal write data bus is 72 bits wide.
 8. Theintegrated circuit device of claim 1 wherein said demultiplexer circuitfurther comprises a write buffer associated therewith.
 9. The integratedcircuit device of claim 1 wherein said multiplexer and demultiplexercircuits are 4 to 1 devices.
 10. The integrated circuit device of claim1 wherein said row register comprises static random access memory. 11.The integrated circuit device of claim 1 wherein said device presents anexternal interface equivalent to a DRDRAM device.
 12. A packet-basedintegrated circuit device including an address bus and internal read andwrite data buses, said device comprising: at least one dynamic randomaccess memory bank; a row decoder associated with each of said at leastone memory banks, said row decoder being coupled to receive a rowaddress on said address bus; a row register associated with each of saidat least one memory banks, said row register for providing at least aportion of a row of data accessed from a selected row of an associatedone of said at least one memory banks to said read data bus in responseto a corresponding row address provided by an associated one of said rowdecoders; a column decoder associated with each of said row registers,said column decoder being coupled to receive a column address on saidaddress bus; and a sense amplifier circuit coupled to said write databus and associated with each of said at least one memory banks andcoupled between said at least one memory bank and an associated one ofsaid row registers, said sense amplifier circuit operative to providedata to be written at a specified location in an associated one of saidat least one memory banks in response to said row and column addresses.13. The device of claim 12 wherein said at least one dynamic randomaccess memory bank comprises a plurality of memory banks, each of saidplurality of memory banks having an associated one of said row decoderscoupled to said address bus.
 14. The device of claim 13 wherein saidplurality of memory banks further comprises one of said row registersassociated with each of said plurality of memory banks.
 15. The deviceof claim 14 wherein said plurality of memory banks further comprises oneof said sense amplifier circuits associated with each of said pluralityof memory banks.
 16. The device of claim 12 wherein data to be providedto said read data bus from said row register is provided to said rowregister by an associated one of said sense amplifier circuits inparallel over a bus coupled to said selected row of said associatedmemory bank.
 17. The device of claim 16 wherein said internal read databus is substantially equal to 72 bits wide.
 18. The device of claim 16wherein said internal write data bus is substantially equal to 72 bitswide.
 19. The device of claim 12 wherein said row register is operativeto retain said at least a portion of said row of data accessed from saidselected row of said associated one of said at least one memory bankswhile power remains supplied to said device.
 20. The device of claim 12wherein said row register is operative to retain said at least a portionof said row of data accessed from said selected row of said associatedone of said at least one memory banks until overwritten by updated datasupplied on said write data bus corresponding to said selected row. 21.The device of claim 20 wherein said updated data may be writtensubstantially concurrently to said row register and said selected row ofsaid memory bank.
 22. The device of claim 12 wherein said row registeris operative to retain said at least a portion of said row of dataaccessed from said selected row of said associated one of said at leastone memory banks until overwritten by another at least a portion of arow of data from an alternatively selected row of said associated one ofsaid at least one memory banks.
 23. The device of claim 12 wherein saidread data bus is coupled only to said row register.
 24. The device ofclaim 12 wherein said write data bus is coupled to said sense amplifiercircuit.
 25. The device of claim 24 wherein said data to be written tosaid device is always written to said memory bank.
 26. The device ofclaim 12 wherein said data to be written to said device is selectivelywritable substantially concurrently to said row register.
 27. The deviceof claim 26 wherein said data to be written to said device isselectively writable substantially concurrently to said row register ifsaid row of data to be written to said associated one of said memorybanks corresponds to said selected row.
 28. The device of claim 12wherein said sense amplifier circuit is selectively decouplable fromsaid associated one of said row registers.
 29. The device of claim 28wherein said sense amplifier circuit is decoupled from said associatedone of said row registers except when said at least a portion of saidrow of data accessed from said selected row of said associated one ofsaid memory banks is being written thereto.
 30. The device of claim 28wherein said at least one dynamic random access memory bank may beprecharged while said sense amplifier circuit is decoupled from saidassociated one of said row registers.
 31. The device of claim 30 whereinsaid at least a portion of said row of data retained in said rowregister may be provided to said read data bus while said memory bank isprecharged.
 32. The device of claim 28 wherein said at least one dynamicrandom access memory bank may be refreshed while said sense amplifiercircuit is decoupled from said associated one of said row registers. 33.The device of claim 30 wherein said at least a portion of said row ofdata retained in said row register may be provided to said read data buswhile said memory bank is refreshed.
 34. A method for accessing dataover read and write data buses in conjunction with a packet-basedintegrated circuit memory device incorporating at least one dynamicrandom access memory bank and an associated row register coupled by anassociated sense amplifier circuit, said method comprising: reading outa row of data from said memory bank by means of said sense amplifiercircuit; storing at least a portion of said row of read out data in saidrow register; decoupling said sense amplifier circuit from said rowregister; precharging said memory bank; and providing said at least aportion of said row of read out data from said row register on said readdata bus substantially concurrently with said step of precharging saidmemory bank.
 35. The method of claim 34 further comprising: writing datato a selected location in said memory bank through said write data busupon completion of said step of precharging; and substantiallyconcurrently reading out said at least a portion of said row of read outdata from said row register on said read data bus if said selectedlocation does not correspond to said row of read out data.
 36. Themethod of claim 34 further comprising: writing data to a selectedlocation in said memory bank through said write data bus upon completionof said step of precharging; recoupling said sense amplifier circuit tosaid row register; and substantially concurrently writing said data tosaid row register through said sense amplifier circuit if said selectedlocation corresponds to said row of read out data.
 37. A method foraccessing data over read and write data buses in conjunction with apacket-based integrated circuit memory device incorporating at least onedynamic random access memory bank and an associated row register coupledby an associated sense amplifier circuit, said method comprising:reading out a row of data from said memory bank by means of said senseamplifier circuit; storing at least a portion of said row of read outdata in said row register; decoupling said sense amplifier circuit fromsaid row register; refreshing said memory bank; and providing said atleast a portion of said row of read out data from said row register onsaid read data bus substantially concurrently with said step ofrefreshing said memory bank.
 38. The method of claim 37 furthercomprising: writing data to a selected location in said memory bankthrough said write data bus upon completion of said step of refreshing;and substantially concurrently reading out said at least a portion ofsaid row of read out data from said row register on said read data busif said selected location does not correspond to said row of read outdata.
 39. The method of claim 37 further comprising: writing data to aselected location in said memory bank through said write data bus uponcompletion of said step of refreshing; recoupling said sense amplifiercircuit to said row register; and substantially concurrently writingsaid data to said row register through said sense amplifier circuit ifsaid selected location corresponds to said row of read out data.
 40. Amethod for accessing data over read and write data buses in conjunctionwith a packet-based integrated circuit memory device incorporating atleast one dynamic random access memory bank and an associated rowregister coupled by an associated sense amplifier circuit, said methodcomprising: coupling said row register through said sense amplifiercircuit to said memory bank; transferring data held in said memory bankto said row register; decoupling said row register from said senseamplifier circuit; and providing said data from said row register onsaid read data bus.
 41. The method of claim 40 further comprising:writing data on said write data bus to said memory bank substantiallyconcurrently with said step of providing said data from said rowregister on said read data bus.
 42. The method of claim 40 furthercomprising: precharging said memory bank substantially concurrently withsaid step of providing said data from said row register on said readdata bus.
 43. The method of claim 40 further comprising: refreshing saidmemory bank substantially concurrently with said step of providing saiddata from said row register on said read data bus.